The present invention relates to a method for manufacturing a semiconductor device that employs an SOI (Silicon On Insulator) substrate, more particularly, to a method for manufacturing a semiconductor device that enhances the capability of an SOI device in fixing the electrical potential of an SOI layer more securely.
In recent years, a semiconductor device in which such elements as transistors are integrated and is used within electronic equipment has been strongly demanded to operate in higher speed and lower power consumption. In order to meet such strong demand, advanced technologies have been developed and the refinement and the reduction in parasitic capacitance of a semiconductor device have been thereby considered effective.
Note that the refinement of a semiconductor device means mainly the reduction in gate length of a MOS transistor. However, the shorter the gate length is, the further enhanced the short channel effect of a MOS transistor is. To prevent the enhancement of short channel effect, the following technology for forming the so-called pocket region has been conceived. That is, impurity ions of the conductivity type opposite to that of the conductivity type of a source/drain region are implanted into the regions located inside the source/drain regions at a tilt angle of 45 degrees with respect to a direction perpendicular to the principal surface of a semiconductor substrate.
In addition, as one of measures to reduce the parasitic capacitance of a semiconductor device, an SOI device has been conceived so that a semiconductor layer is formed on an insulating substrate and then a semiconductor device such as a transistor is formed in the semiconductor layer. However, there also has been found many difficult problems that were not solved by the conventional technology being fostered in the semiconductor device development employing a bulk semiconductor substrate.
A conventional SOI device consisting of CMOS transistor with a pocket region will be described below. FIG. 7 is a cross sectional view of a conventional SOI device taken along a line in a channel direction (gate length direction).
As shown in FIG. 7, the CMOS type conventional SOI device comprises a silicon substrate 103, a BOX (Buried Oxide) layer 104 formed in a region having a certain depth below the principal surface of the silicon substrate 103,an oxide film 106 for element isolation formed as an STI (Shallow Trench Isolation) to separate a semiconductor layer 105 located on the BOX layer 104 into an n-type MISFET formation region denoted by Rnt and a p-type MISFET formation region denoted by Rpt, a gate insulating film 107 of a silicon oxide film formed on the semiconductor layer 105, a gate electrode 108 formed on the gate insulating film 107, a silicide layer 108a formed in the upper portions of the gate electrode 108, and sidewalls 110 of a silicon oxide film formed on the side surfaces of the gate electrode 108.
Furthermore, an n-type MISFET comprises, within the semiconductor layer 105, n-type source/drain regions 111 formed in both regions beside the gate electrode 108, silicide layers 111a formed in the upper portions of the n-type source/drain regions 111, n-type LDD regions 113 formed inside the n-type source/drain regions 111, p-type pocket regions 112 formed under the n-type LDD regions 113 and located inside the n-type source/drain regions 111, a channel control region 114 including p-type impurities and formed just below the gate insulating film 107, being interposed between the n-type LDD regions 113, and a p-type well region 115 formed under the channel control region 114 so as to extend downward therefrom.
A p-type MISFET comprises, within the semiconductor layer 105, p-type source/drain regions 119 formed in both regions beside the gate electrode 108, silicide layers 119a formed in the upper portions of the p-type source/drain regions 119, p-type LDD regions 121 formed inside the p-type source/drain regions 119, n-type pocket regions 120 formed under the p-type LDD regions 121 and located inside the p-type source/drain regions 119, a channel control region 122 including n-type impurities and formed just below the gate insulating film 107, being interposed between the p-type LDD regions 121, and an n-type well region 123 formed under the channel control region 122 so as to extend downward therefrom.
It should be noted that in the n-type MISFET formation region, Rnt, as the p-type pocket region 112 is formed under the n-type LDD region 113 doped with impurities at a low concentration, the pocket region suppresses the spread of the depletion layer of the LDD region 113 in the p-type well region 115, whereby the short channel effect generated in the n-type MISFET is suppressed.
In the same manner as in the n-type MISFET, in the p-type MISFET formation region, Rpt, as the n-type pocket region 120 is formed under the p-type LDD region 121 doped with impurities at a low concentration, the pocket region suppresses the spread of the depletion layer of the LDD region 121 in the n-type well region 123, whereby the short channel effect generated in the p-type MISFET is suppressed.
However, in the SOI device as above, each of the MISFET formation regions is isolated from each other by the BOX layer 104 and the oxide film 106 for element isolation formed as an STI. Owing to the specific structure of the SOI device described above, the electrical potential of the body regions right under the channel control region 114 of the n-type MISFET and that of the body regions right under the channel control region 122 of the p-type MISFET cannot be fixed via respective well regions 115 and 123, whereas the electrical potential of a body region in a bulk silicon device employing a bulk silicon substrate is fixed. To prevent such phenomenon, in general, a body contact region shown in the following explanation is formed to fix the electrical potential of a body region.
FIG. 8A is a plan view of a CMISFET that consists of the n-type MISFET and the p-type MISFET shown in FIG. 7, and simultaneously constitutes an inverter circuit. FIG. 8B is a cross sectional view of the CMISFET taken along a line orthogonal to a channel direction. However, note that in FIG. 8A sidewalls 110 are omitted for simplicity of illustration.
As shown in FIGS. 8A and 8B, a p-type body contact region 131 doped with p-type impurities at a high concentration and a silicide film 131a are formed in the n-type MISFET formation region, Rnt. This p-type body contact region 131 is formed to fix the electrical potential of the p-type well region 115 right under the channel control region 114 of the n-type MISFET and reduce substantially the resistance of the p-type well region. In addition, in the same manner as in the n-type MISFET, an n-type body contact region 141 doped with n-type impurities at a high concentration and a silicide film 141a are formed in the p-type MISFET formation region, Rpt. This n-type body contact region 141 is formed to fix the electrical potential of the n-type well region 123 right under the channel control region 122 of the p-type MISFET and reduce substantially the resistance of the n-type well region.
Furthermore, plugs 129 penetrating an interlayer insulating film 128 are formed therein reaching the surfaces of the gate electrode 108, the source/drain regions 111, 119 and the body contact regions 131, 141, whereby each of the above-stated portions are supplied with a voltage via the plugs 129. In more detail, the body contact regions 131 and 141 are connected to the well regions 115 and 123 respectively via the corresponding pathway portions, and thus by supplying a voltage to the plugs 129 that reach the surfaces of the body contact regions 131 and 141, the inverter circuit is configured to fix the electrical potential of the well regions 115 and 123 just below the channel control regions 114 and 122, respectively.
However, in the above-described conventional SOI device, there has been seen a problem that even when a voltage is applied to the respective body contact regions 131 and 141 via the corresponding plugs 129 in the n-type MISFET and the p-type MISFET, the electrical potential of the well regions 115 and 123 just below the respective channel control regions 114 and 122 of the MISFETs is not securely being fixed.
So, the inventor investigated the cause of the problem and then obtained the result that the following phenomenon occurs in the inverter circuit of the conventional SOI device.
First, low concentration impurities are in advance being introduced into the well regions 115 and 123 of the respective MISFETs, thereby forming the n-type MISFET formation regions, Rnt, doped with p-type impurities at a low concentration and the p-type MISFET formation region, Rpt, doped with n-type impurities at a low concentration, respectively, within the semiconductor layer 105. Subsequently, impurity introduction for controlling a threshold voltage (channel doping method) is performed to form the channel control regions 114 and 122 in the respective MISFETs.
Thereafter, in the n-type MISFET formation region, Rnt, an impurity ion-implantation is carried out to form the p-type body contact region 131, simultaneously forming source/drain regions 119 of the p-type MISFET. That is, impurity ions are implanted through a first opening 150a (NW opening), indicated by the alternate long and short dash line in FIG. 8A, of an ion-implantation mask into the p-type body contact region 131 of the n-type MISFET, and the impurity ions are implanted through a second opening 150b (ND opening), indicated by the alternate long and short dash line, of the ion-implantation mask into the source/drain regions 119 of the p-type MISFET.
In the same manner, in the p-type MISFET formation region, Rpt, an impurity ion-implantation is carried out to form the n-type body contact region 141, simultaneously forming source/drain regions 111 of the n-type MISFET. That is, impurity ions are implanted through a first opening 160a (PW opening), indicated by the alternate long and two short dash line in FIG. 8A, of another ion-implantation mask into the n-type body contact region 141 of the p-type MISFET, and the impurity ions are implanted through a second opening 160b (PD opening), indicated by the alternate long and two short dash line, of the another ion-implantation mask into the source/drain regions 111 of the n-type MISFET.
At this stage where the above-stated processes are completed, in the n-type MISFET formation region, Rnt, the p-type body contact region 131 and the p-type well region 115 are considered to fundamentally be electrically connected to each other since both regions 131 and 115 have a common conductivity type. Similarly, in the p-type MISFET formation region, Rpt, the n-type body contact region 141 and the n-type well region 123 are considered to fundamentally be electrically connected to each other since both regions 141 and 123 have a common conductivity type. Therefore, it has been considered possible that the body electrical potential of the MISFETs is fixed by supplying a voltage to the body contact regions 131 and 141 via the respective plugs 129.
However, the above-stated consideration is not the case. The fact is as follows: in the conventional process for forming a CMISFET, the ion-implantation mask used for forming a source/drain region is also used to perform an impurity ion-implantation (pocket ion-implantation) to form a pocket region. Here, it should be noted the reason why such manufacturing method has been employed in the conventional manufacturing process for an SOI device is that, in order to lower the manufacturing cost, the number of photolithography steps has to be reduced as many as possible in the whole manufacturing process steps. When the n-type pocket region (the region 120 illustrated in FIG. 7) of the p-type MISFET is going to be formed, four-step ion-implantations (hereinafter, the words xe2x80x9cfour-step ion-implantationsxe2x80x9d are used for ion-implantations done from each of four sides of a wafer) of n-type impurity ions are carried out at a tilt angle of 45 degrees with respect to a direction perpendicular to the substrate surface.
As illustrated in FIG. 8B, when the above-stated pocket ion-implantation for the p-type MISFET is carried out in the n-type MISFET formation region, Rnt, the n-type impurities implanted through the first opening 150a are introduced into the pathway portion and thus an n-type region 132 is formed within the pathway portion that connects the p-type well region 115 and the p-type body contact region 131. The reason for the formation of the n-type region 132 is that although the concentration of the n-type impurities implanted in this ion-implantation step is lower than the p-type impurity concentration of the p-type body contact region 131, it is higher than the impurity concentration of the p-type well region 115. Here, it should be noted that the pocket ion-implantation to be done almost exclusively for forming the pocket regions of the p-type MISFET shown in FIG. 8A does not contribute to the formation of the n-type region 132 of the n-type MISFET formation region, Rnt, shown in FIG. 8B, but the pocket ion-implantation to be done almost exclusively for forming pocket regions of other p-type MISFETs, each having a gate electrode orthogonal to the gate electrode 108 shown in FIG. 8A, contributes to the formation of the n-type region 132 shown in FIG. 8B.
For the similar reason explained in the case of the formation of the n-type region 132, when the pocket ion-implantation for the n-type MISFET is carried out, the p-type impurities implanted through the first opening 160a are introduced into the pathway portion and thus a p-type region 142 is formed within the pathway portion that connects the n-type well region 123 and the n-type body contact region 141.
Consequently, it is considered that the regions, each having the conductivity type opposite to that of the corresponding body contact regions 131 and 141, are formed within the respective pathway portions that connect the body contact regions 131, 141 and the well regions 115, 123, respectively, and as a result, the regions become to lie between the body contact regions 131, 141 and the well regions 115, 123, respectively, whereby the body electrical potential of the MISFETs is not fixed securely.
Furthermore, when an ion-implantation is carried out to form the p-type LDD regions of the p-type MISFET, a low concentration p-type region 143 is simultaneously formed in the upper portion of the pathway portion that connects the n-type body contact region 141 and the n-type well region 123. Similarly, when an ion-implantation is carried out to form the n-type LDD regions of the n-type MISFET, a low concentration n-type region 133 is simultaneously formed in the upper portion of the pathway portion that connects the p-type body contact region 131 and the p-type well region 115. By these configurations of the MISFETs, the conventional SOI device is in danger of lowering its capability of fixing the body electrical potential of the MISFETs since the resistance of the pathway portions increases in accordance with the narrowed width of the pathway portions.
It is an object of the present invention to provide a manufacturing method for preventing impurity ions of the conductivity type opposite to that of a body contact region from being implanted into a pathway portion that connects the well region and the body contact region of a MISFET formation region, whereby an SOI device becomes to have high capability of fixing a body electrical potential while responding to the requirement for further refinement of an SOI device.
Before describing a method for manufacturing a semiconductor device of the present invention, the semiconductor device manufactured by this method is assumed to have a configuration as follows: a semiconductor device comprising:
a first MISFET having:
a gate electrode formed on a semiconductor layer of an SOI substrate;
source/drain regions of a first conductivity type formed in both regions beside the gate electrode in the semiconductor layer;
a well region of a second conductivity type formed below the gate electrode in the semiconductor layer;
pocket regions doped with impurities of the second conductivity type at a higher concentration than that of the well region and formed between the well region and the source/drain regions in the semiconductor layer;
a body contact region doped with impurities of the second conductivity type at a higher concentration than that of the well region and connected to the well region;
a pathway portion doped with impurities of the second conductivity type and connecting the well region and the body contact region;
a second MISFET having:
the gate electrode formed on the semiconductor layer of the SOI substrate;
source/drain regions of the second conductivity type formed in both regions beside the gate electrode in the semiconductor layer;
a well region of the first conductivity type formed below the gate electrode in the semiconductor layer;
pocket regions doped with impurities of the first conductivity type at a higher concentration than that of the well region and formed between the well region and the source/drain regions in the semiconductor layer;
a body contact region doped with impurities of the first conductivity type at a higher concentration than that of the well region and connected to the well region;
a pathway portion doped with impurities of the first conductivity type and connecting the well region and the body contact region.
Subsequently, the method for manufacturing the above-described semiconductor device comprises a pocket ion-implantation step for implanting impurity ions of the second conductivity type into the pocket regions of the first MISFET by using a first ion-implantation mask covering the body contact region of the second MISFET, and implanting impurity ions of the first conductivity type into the pocket region of the second MISFET by using a second ion-implantation mask covering the body contact region of the first MISFET.
By applying this method, the impurities of the first conductivity type to be implanted for forming the pocket regions of the second MISFET is never introduced into the pathway portion that connects the body contact region and the well region of the first MISFET, and further the impurities of the first conductivity type to be implanted for forming the pocket region of the first MISFET is never introduced into the pathway portion that connects the body contact region and the well region of the second MISFET. Therefore, the body electrical potential can be securely fixed since the impurities of the same conductivity type are doped thoroughly from the body contact region to the well region in the first and second MISFETs, respectively.
The above-described semiconductor device may have a further configuration as follows:
the gate electrode extends to cover halfway portions of the pathway portions of the corresponding well regions;
within the semiconductor layer, each of the first and second MISFETs further comprises second source/drain regions doped with impurities of the same conductivity type as the source/drain regions at a lower concentration than that of the source/drain regions and being adjacent to the respective source/drain regions on sides near the gate electrode.
Under the above-described configuration, when the first and second ion-implantation masks are also applied for implanting impurity ions to form the respective second source/drain regions, the first and second ion-implantation masks may cover a part of the respective pathway portions of the well regions, the part being not covered by the gate electrode. This prevents impurities of the conductivity type opposite to that of the pathway portion to be ion-implanted for forming the second source/drain regions in the respective MISFETs from being introduced into the pathway portions of the respective MISFETs, whereby the phenomenon that the capability of the inverter circuit in fixing the electrical potential of the body degrades can be prevented.
The method for manufacturing the semiconductor device is still further configured as follows. That is, when impurity ions of the second conductivity type are implanted into the body contact region of the first MISFET, a third ion-implantation mask covering an adjacent part of the body contact region to the pathway portion may be applied, and when impurity ions of the first conductivity type are implanted into the body contact region of the second MISFET, a fourth ion-implantation mask covering an adjacent part of the body contact region to the pathway portion may be applied. Thereby the length of the pathway portions can be made as short as possible and thus the finer pattern of a semiconductor device can be achieved.